The peripheral circuits of switching power supplies have become quite simplified with technological development, especially DC-DC power supply systems, which typically consist of only a few components such as chips, inductors, Schottky diodes, capacitors and resistors, appearing simple and easy to use.
The peripheral circuits of switching power supplies have become quite simplified with technological development, especially DC-DC power supply systems, which typically consist of only a few components such as chips, inductors, Schottky diodes, capacitors and resistors, appearing simple and easy to use. However, many engineers have encountered various problems in practical applications—even when manufacturing products according to the circuits provided by the original factory, issues such as abnormal system load capacity, inductor noise, unstable output voltage or excessive ripple, and product failures after a period of operation in mass production may occur.
Ordinarily, the above malfunctions are all caused by failing to follow switching power supply routing rules when designing the PCB in the early stage. The lowest-risk and optimal method for product design is to directly copy the circuit traces from the DEMO board to the product. However, this approach is not feasible in practice due to various reasons, requiring engineers to reposition components and reroute the PCB.
This article takes the Figure 1. Typical XL6007 Circuit as an example to briefly introduce the PCB routing considerations for BOOST topology circuits.
Step 1: Placement of Output Capacitor and Schottky Diode
For BOOST topology circuits, the output current is discontinuous. According to the formula V=L×di/dt, the changing current will generate glitch voltage on parasitic inductance. If not properly addressed, this glitch voltage will affect system stability and even cause IC failure.
Under fixed operating conditions, di/dt is basically constant, so the only way to reduce the glitch voltage is to lower the parasitic inductance in the switching current loop. To reduce parasitic inductance, the length of the current loop must be minimized. The method to shorten the switching current loop is as follows:
- Place the positive pole of the output electrolytic capacitor close to the cathode of the Schottky diode;
- Place the negative pole of the output electrolytic capacitor close to the GND pin of the chip;
- Place the SW pin of the chip close to the anode of the Schottky diode.
This layout minimizes parasitic inductance, reduces glitch voltage, improves system stability, and lowers radiated EMI.
Step 2: Placement of Inductor and Input Capacitor
For switching power supplies, the input end usually uses a combination of electrolytic and ceramic capacitors (mainly for cost-effectiveness), which serve energy storage and filtering functions:
- Electrolytic capacitors supply transient current to the chip to prevent large fluctuations in input voltage;
- Ceramic capacitors filter high-frequency glitch voltage at the input end and provide a clean power supply for the internal logic circuit of the chip.
Therefore, in the layout:
- Place ceramic capacitors close to the VIN and GND pins of the chip, and avoid connecting them via vias (vias generate parasitic inductance that seriously impairs the filtering effect of ceramic capacitors);
- To reduce noise and electromagnetic radiation in the system loop, not only shorten the switching current loop but also the high-current loop;
- Use copper pouring for high-current traces, avoid acute angles and excessive bends, and minimize layer transitions. If layer transitions are inevitable, appropriately increase the number of vias to reduce parasitic inductance from vias;
- Place the inductor close to the chip's SW pin, and the input capacitor close to the inductor and the chip's GND pin.
Step 3: Placement and Routing of Feedback Resistors
Feedback routing is also critical in the system loop—the FB pin is responsible for adjusting and stabilizing the output voltage. To prevent the FB pin from picking up noise from the circuit, the FB pin node should be minimized as much as possible. For the FB node:
- Place the voltage divider resistors close to the FB and GND pins of the chip;
- Route the feedback traces away from switching nodes such as inductors, Schottky diodes and SW pins;
- Ideally, surround the feedback traces with GND traces for shielding.
Supplementary Note
Some engineers use single-layer routing for PCB design to cut costs. Although single-layer PCBs reduce PCB costs, they are unfavorable for PCB routing, leading to longer high-current trace loops. Additionally, traces of the same length on a single-layer PCB generate more than 10 times the parasitic inductance compared to those on a double-layer PCB. Excessive parasitic inductance produces severe glitch voltage that impairs system performance and shortens service life.
It is recommended to use double-layer PCBs for design and appropriately increase the number of vias to reduce parasitic parameters of vias.
Table 1: Parasitic Inductance Comparison of Traces (50mm in length)
| PCB Type |
h (mm) |
Wg (mm) |
L (nH) |
| Single-layer |
- |
- |
52 |
| Double-layer |
1.2 |
10 |
3.8 |
| Four-layer |
0.4 |
10 |
- |
Note: h = Insulation thickness between traces; Wg = Width of the corresponding ground trace; L = Parasitic inductance.
