Vias are one of the key components of multi-layer PCBs, and drilling costs typically account for 30% to 40% of total PCB fabrication expenses. Simply put, every hole on a PCB can be referred to as a via.
Vias are one of the key components of multi-layer PCBs, and drilling costs typically account for 30% to 40% of total PCB fabrication expenses. Simply put, every hole on a PCB can be referred to as a via.
Basic Concept of Vias
In terms of function, vias are classified into two categories:
- Electrical interconnection between different layers
- Fixing or positioning of components
From a manufacturing process perspective, vias are generally divided into three types: blind vias, buried vias, and through-hole vias.
- Blind vias are located on the top and bottom surfaces of a PCB, with a specified depth. They are used to connect surface traces to underlying inner-layer traces, and the depth of the hole usually does not exceed a certain ratio relative to the hole diameter.
- Buried vias are connecting holes located in the inner layers of a PCB and do not extend to the board surface.
Both blind and buried vias are formed in inner layers using through-hole molding processes before lamination, and multiple inner layers may be overlapped during via formation.
- Through-hole vias penetrate the entire PCB and can be used for internal interconnection or component mounting/positioning.
Through-hole vias are easier to manufacture and lower in cost, so they are adopted in most PCBs instead of the other two types. Unless otherwise specified, all vias mentioned below refer to through-hole vias.
From a design perspective, a via consists of two main parts:
- The central drilled hole
- The pad area surrounding the drilled hole
The dimensions of these two parts determine the overall size of the via.
In high-speed, high-density PCB design, engineers always prefer smaller vias to reserve more routing space on the board. In addition, smaller vias have lower parasitic capacitance, making them more suitable for high-speed circuits.
However, reducing via size increases manufacturing cost, and via dimensions cannot be reduced indefinitely due to process limitations such as drilling and electroplating:
- Smaller holes require longer drilling time and are more prone to off-center misalignment.
- When the depth of the hole exceeds 6 times the drill diameter, uniform copper plating on the hole wall cannot be guaranteed.
For example, a standard 6-layer PCB has a thickness (through-hole depth) of 50 mils; under normal conditions, PCB manufacturers can only provide a minimum drill diameter of 8 mils. With the development of laser drilling technology, via sizes can be further reduced. Vias with a diameter of ≤6 mils are defined as microvias.
Microvias are widely used in HDI (High-Density Interconnect) design. Microvia technology allows vias to be drilled directly on pads, greatly improving circuit performance and saving routing space.
Vias act as impedance-discontinuity breakpoints on transmission lines and cause signal reflection. The equivalent impedance of a typical via is approximately 12% lower than that of the transmission line. For example, the impedance of a 50-ohm transmission line decreases by 6 ohms when passing through a via (the exact value varies with via size and board thickness, and is not a fixed reduction).
However, the reflection caused by via impedance discontinuity is negligible, with a reflection coefficient of only:
(44-50)/(44+50) = 0.06
The main problems caused by vias are concentrated in the effects of parasitic capacitance and parasitic inductance.
Parasitic Capacitance and Inductance of Vias
Vias inherently have stray parasitic capacitance. Given the anti-pad diameter of the via on the copper pour layer is D2, the via pad diameter is D1, the PCB thickness is T, and the dielectric constant of the board substrate is ε, the parasitic capacitance of the via can be approximated by the formula:
C = 1.41εTD1/(D2-D1)The primary impact of via parasitic capacitance is slowing down the signal rise time and reducing circuit speed.
Example: For a 50-mil thick PCB using a via with a 20-mil pad diameter (10-mil drill diameter) and a 40-mil anti-pad diameter, the parasitic capacitance is calculated as:
C = 1.41×4.4×0.050×0.020/(0.040-0.020) = 0.31 pF
The change in rise time caused by this capacitance is approximately:
T₁₀₋₉₀ = 2.2C(Z₀/2) = 2.2×0.31×(50/2) = 17.05 psAlthough the slowdown of rise time caused by a single via’s parasitic capacitance is not significant, multiple vias used for layer switching in routing must be carefully considered in design. Parasitic capacitance can be reduced in practice by increasing the distance between the via and copper pour area (anti-pad) or decreasing the pad diameter.
Vias have both parasitic capacitance and parasitic inductance. In high-speed digital circuit design, the harm caused by via parasitic inductance is often greater than that of parasitic capacitance. Its series parasitic inductance weakens the effectiveness of bypass capacitors and reduces the filtering performance of the entire power supply system.
The approximate parasitic inductance of a via can be simply calculated using the following empirical formula:
L = 5.08h[ln(4h/d)+1]
Where:
- L = inductance of the via
- h = length of the via
- d = diameter of the central drilled hole
The formula shows that via diameter has little effect on inductance, while via length has the greatest impact. Using the previous example, the via inductance is calculated as:
L = 5.08×0.050[ln(4×0.050/0.010)+1] = 1.015 nH
If the signal rise time is 1 ns, the equivalent impedance is:
X_L = πL/T₁₀₋₉₀ = 3.19 ΩThis impedance cannot be ignored when high-frequency current passes through. Notably, bypass capacitors require two vias to connect power and ground planes, which doubles the parasitic inductance of the vias.
How to Use Vias
Based on the above analysis of via parasitic characteristics, seemingly simple vias can often bring significant negative effects to circuit design in high-speed PCBs. To minimize the adverse impacts of via parasitics, the following practices are recommended in design:
- Select reasonable via sizes by balancing cost and signal quality. Use different via sizes when necessary: larger vias for power/ground to reduce impedance, and smaller vias for signal traces. Note that smaller vias increase cost.
- As derived from the two formulas above, using a thinner PCB helps reduce both parasitic parameters of vias.
- Minimize layer switching for signal traces on the PCB, i.e., avoid using unnecessary vias.
- Place vias close to power and ground pins; keep the leads between vias and pins as short as possible. Multiple parallel vias can be used to reduce equivalent inductance.
- Place ground vias near signal layer-switching vias to provide the closest return path for signals. Additional ground vias can be placed on the PCB if needed.
- Consider using microvias for high-density high-speed PCBs.
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