Electromagnetic Compatibility Design in PCB Stackup and Layer Partitioning

For multilayer printed circuit boards (PCBs), superior electromagnetic compatibility (EMC) design is essential to ensure the boards comply with EMC and susceptibility standards during normal operation. A proper stackup helps shield and suppress electromagnetic interference (EMI).

EMC analysis of multilayer PCBs can be based on Kirchhoff's Laws and Faraday's Law of Electromagnetic Induction.

Based on the above two laws, the following basic principles must be followed in layer partitioning and stackup of multilayer PCBs: ① Power planes shall be placed as close to ground planes as possible and located beneath the ground planes. ② Routing layers shall be arranged adjacent to their reference planes. ③ Impedance of power and ground planes: The power plane impedance Z₀ is related to D (spacing between power and ground planes) and W (area between the planes). ④ Striplines are formed in inner layers, and microstrip lines are formed on the surface; the two have different electrical characteristics. ⑤ Critical signal traces shall be placed close to ground planes.

This type of board is only suitable for low-speed designs and exhibits poor EMC performance.

Several stackup sequences are available, with the advantages and disadvantages of each configuration explained below.

Note: S1 = 1st signal routing layer; S2 = 2nd signal routing layer; GND = Ground plane; POWER = Power plane

Configuration A is a preferred option for 4-layer boards. The outer ground planes provide EMI shielding, and the close placement of power and ground planes reduces power supply impedance for optimal performance. However, this configuration is not suitable for high-density boards, as it compromises the integrity of inner ground planes and degrades signal quality on Layer 2. It is also not applicable to boards with high power consumption.

Configuration B is a commonly used structure in general designs but is unsuitable for high-speed digital circuits, as it is difficult to maintain low power supply impedance. Taking a 2 mm-thick board as an example: to achieve Z₀ = 50 Ω with 8 mil trace width and 35 μm copper foil thickness, the dielectric thickness between Layer 1 (signal) and Layer 2 (ground) is 0.14 mm, while the spacing between ground and power planes reaches 1.58 mm.

This greatly increases power supply impedance. Radiated emissions propagate into free space in this structure, requiring additional shielding plates to reduce EMI.

Configuration C provides good signal quality on Layer S1 and acceptable quality on Layer S2, with certain EMI shielding effects. However, power plane impedance is relatively high. This board is suitable for high-power-consumption applications where the board acts as an interference source or is placed close to an interference source.

Configuration A is a common stackup; Layer S1 is an optimal routing layer, followed by Layer S2. However, power plane impedance is suboptimal. Routing shall consider the crosstalk between Layer S2 and Layer S3.

Configuration B provides excellent routing quality on Layer S2, followed by Layer S3, with favorable power plane impedance.

Configuration C is the optimal stackup for 6-layer boards, with Layers S1, S2, and S3 all being high-quality routing layers and good power plane impedance. The only drawback is one fewer routing layer compared with the previous two configurations.

Configuration D outperforms the first three in electrical performance but has fewer routing layers. It is mostly used for backplane applications.

For an 8-layer board requiring 6 signal layers, Configuration A is preferred but is not suitable for high-speed digital circuit designs.

For 5 signal layers, Configuration C is optimal, with Layers S1, S2, and S3 as high-quality routing layers and low power plane impedance.

For 4 signal layers, Configuration B is the best choice, with all signal layers offering excellent routing performance. Adjacent signal layers shall use orthogonal routing in all the above configurations.

For a 10-layer board with 6 signal layers, Configurations A, B, and C are available. Configuration A is optimal, followed by Configuration C, while Configuration B is the least favorable. Other unlisted configurations perform even worse.

In Configuration A, Layers S1 and S6 are excellent routing layers, followed by Layers S2, S3, and S5. Notably, Configuration A outperforms Configuration C mainly because the spacing between the ground and power planes in Configuration C is determined by the distance between Layer S5 and the ground plane, which cannot guarantee the impedance of the power-ground plane pair.

Configuration D features the best overall performance for 10-layer boards, with all signal layers being high-quality routing layers.

Configurations E and F are mostly used for backplanes. Configuration F provides better EMC shielding than Configuration E, but care must be taken during routing as adjacent signal layers are prone to crosstalk.

In summary, PCB layer partitioning and stackup is a complex task involving multiple factors. Designers shall always focus on the required functions and critical performance indicators to determine the optimal stackup sequence for the PCB.

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