Motor driver ICs carry large currents while dissipating significant electrical energy, which is typically transferred to the copper pouring areas of the Printed Circuit Board (PCB). Special PCB design techniques are required to ensure adequate cooling of the PCB. In the first part of this article, we provide general PCB design recommendations for motor driver ICs.
Motor driver ICs carry large currents while dissipating significant electrical energy, which is typically transferred to the copper pouring areas of the Printed Circuit Board (PCB). Special PCB design techniques are required to ensure adequate cooling of the PCB. In the first part of this article, we provide general PCB design recommendations for motor driver ICs.
Use Large-Area Copper Pouring!
Copper is an excellent thermal conductor, whereas the PCB substrate material (FR-4 glass epoxy resin) is a poor thermal conductor. From a thermal management perspective, more copper pouring area on the PCB results in better heat conduction.
For example, thick copper boards of 2 oz (68 μm thickness) offer better thermal conductivity than thin copper boards. However, thick copper is expensive and difficult to form fine geometries, so 1 oz (34 μm thickness) copper boards are commonly selected. Outer layers often use 1/2 oz plated copper, which can reach 1 oz thickness after plating.
Inner layers of multilayer boards usually adopt solid copper planes for enhanced heat dissipation. However, since these planes are typically located at the center of the PCB stackup, heat may be trapped inside the board. To address this, additional copper pouring areas can be added on the outer layers of the PCB and connected to the inner layers with vias to transfer heat outward.
Heat dissipation is more challenging for double-layer PCBs due to traces and components. Therefore, motor driver ICs should utilize as many solid copper planes and heat-dissipating vias as possible. Copper should be poured on both sides of the outer layers and connected with vias to distribute heat across different areas separated by traces and components.
Traces Must Be Wide – The Wider, The Better!
Given the large currents (sometimes exceeding 10 A) flowing through motor driver ICs, the width of PCB traces connecting to the chips must be carefully considered. Wider traces have lower resistance; the trace width must be optimized to prevent excessive energy dissipation from trace resistance, which causes temperature rise. Overly narrow traces act like fuses and are prone to burnout.
Designers typically use the IPC-2221 standard to calculate appropriate trace widths. This specification includes charts showing copper cross-sectional areas for different current levels and allowable temperature rises, from which trace widths can be converted for a given copper layer thickness. For instance, a 7 mm-wide trace is required to carry 10 A current with a 10 °C temperature rise on a 1 oz copper layer, while only a 0.3 mm trace is needed for 1 A current.
Extrapolating with this method may suggest that 10 A current cannot be routed through miniature IC pads.
It is important to note that the IPC-2221 standard provides recommendations for long PCB traces of constant width. A short segment of PCB trace can carry higher current without adverse effects if connected to a wider trace or copper pouring area.
This is because short and narrow PCB traces have very low resistance, and the heat they generate is absorbed into the wider copper pouring areas. As shown in the example in Figure 1: even though the thermal pad of the device is only 0.4 mm wide, it can carry a continuous current of up to 3 A because the trace is widened as close to the actual device width as possible.
Since heat generated by narrow traces is conducted to wider copper pouring areas, the temperature rise of narrow traces is negligible.
Traces embedded in inner PCB layers have poorer heat dissipation than outer-layer traces due to the low thermal conductivity of insulating materials. For this reason, inner-layer trace widths should be twice that of outer-layer traces.
Table 1 provides approximate recommended widths for long traces (> 2 cm) in motor driver applications.
| Current (RMS or DC) |
Trace Width for 1 oz Copper Pouring |
|
Trace Width for 2 oz Copper Pouring |
|
|
Outer Layer |
Inner Layer |
Outer Layer |
Inner Layer |
| ≤1 A |
0.6 mm |
1.2 mm |
0.3 mm |
0.6 mm |
| 2.5 A |
1 mm |
2 mm |
0.5 mm |
1 mm |
| 5 A |
2.5 mm |
5 mm |
1.2 mm |
2.5 mm |
| 10 A |
7 mm |
14 mm |
3.5 mm |
7 mm |
If space permits, wider traces or copper pouring minimize temperature rise and voltage drop.
Thermal Vias – The More, The Better!
Vias are small plated holes typically used to route signal traces between layers. As the name implies, thermal vias transfer heat between layers. Proper use of thermal vias effectively aids PCB heat dissipation, but many practical manufacturing considerations must be taken into account.
Vias have thermal resistance, meaning a temperature difference exists across the via when heat flows through it, measured in °C/W. To minimize thermal resistance and maximize heat dissipation efficiency, vias should be designed larger with greater copper plating area inside the hole (see Figure 2).
While large vias can be used in open PCB areas, vias are often placed inside thermal pads to dissipate heat directly from the IC package. In this case, large vias are not feasible, as oversized plated holes cause solder bleed – solder used to bond the IC to the PCB flows down into the through-hole, resulting in poor solder joints.
Several methods reduce solder bleed. One is to use very small vias to minimize solder flow into the holes. However, smaller vias have higher thermal resistance, so more small vias are required to achieve the same heat dissipation performance.
Another technique is to tent vias on the board backside. This involves removing the solder mask opening on the back layer so that solder mask material covers the vias. The solder mask seals small vias and prevents solder from wicking into the PCB.
This introduces another issue: flux entrapment. If solder mask covers vias, flux becomes trapped inside. Some flux formulations are corrosive and can compromise chip reliability if left uncleaned. Fortunately, most modern no-clean flux processes are non-corrosive and do not cause problems.
Note that thermal vias do not dissipate heat on their own – they must be directly connected to copper pouring areas (see Figure 3).
PCB designers are advised to consult with SMT process engineers at PCB assembly houses to determine the optimal via size and structure, especially when vias are located inside thermal pads.
Soldering Thermal Pads
TSSOP and QFN packages feature large thermal pads on the bottom of the chip, directly connected to the back of the die to dissipate heat from the device. The pad must be properly soldered to the PCB to dissipate power effectively.
IC datasheets do not always specify solder paste openings for thermal pads. SMT process engineers typically have their own rules for solder volume and stencil aperture shapes for vias.
Using an aperture matching the pad size requires more solder; when molten, surface tension can lift the device, causing tombstoning. It also leads to solder voids (internal cavities or gaps in the solder), formed when volatile flux components evaporate or boil during reflow, causing solder depletion in the joint.
To resolve these issues, solder paste is usually deposited in multiple small square or circular areas for pads larger than approximately 2 mm² (see Figure 4). Distributing solder across multiple smaller areas allows volatile flux components to escape more easily, preventing solder depletion.
Again, PCB designers are advised to consult with SMT process engineers to determine the correct thermal pad stencil apertures, and refer to online technical papers for guidance.
Component Placement
Component placement guidelines for motor driver ICs are identical to those for other power ICs. Bypass capacitors should be placed as close to the device power pins as possible, alongside bulk capacitors. Many motor driver ICs use bootstrap or charge-pump capacitors, which should also be placed near the IC.
Refer to the component placement example in Figure 5, which shows the double-layer PCB layout for the MP6600 stepper motor driver. Most signal traces are routed directly on the top layer. Power traces route from bulk capacitors to bypass capacitors, with multiple vias on the bottom layer for layer transitions.
In the second part of this article, we will discuss detailed packaging methods and PCB layouts for motor driver ICs.
Part 2
The first part of this article provided general recommendations for PCB design with motor driver ICs, emphasizing careful layout to achieve proper performance. In this second part, we offer specific PCB layout recommendations for motor drivers with typical packages.
Leaded Package Layout
Standard leaded packages (e.g., SOIC and SOT-23) are commonly used for low-power motor drivers (see Figure 6).
To maximize power dissipation capability of leaded packages, Monolithic Power Systems (MPS) adopts a flip-chip leadframe structure (see Figure 7). Without using bond wires, the die is bonded to the metal leadframe via copper bumps and solder, allowing heat to transfer from the die to the PCB through the leads.
Thermal performance is optimized by connecting large copper areas to high-current-carrying leads. On motor driver ICs, power, ground, and output pins are typically connected to copper areas.
Figure 8 shows a typical PCB layout for the flip-chip leadframe SOIC package. Pin 2 is the device power pin; note the copper area placed near the top-layer device, with several thermal vias connecting this area to the back copper layer of the PCB. Pin 4 is the ground pin, connected to the top-layer ground copper pouring area. Pin 3 (device output) is also routed to a large copper area.
QFN and TSSOP Packages
The TSSOP package is rectangular with two rows of pins. TSSOP packages for motor driver ICs usually feature a large exposed pad at the bottom of the package to dissipate heat from the device (see Figure 9).
The QFN package is a leadless package with pads around the device perimeter and a larger central pad at the bottom of the device (see Figure 10), which absorbs heat from the chip.
To dissipate heat from these packages, the exposed pad must be properly soldered. The exposed pad is typically at ground potential and can be connected to the PCB ground plane. The example in Figure 11 for the TSSOP package uses an 18-via array with a 0.38 mm drill diameter, yielding a calculated thermal resistance of approximately 7.7 °C/W.
These thermal vias usually use a drill diameter of 0.4 mm or smaller to prevent solder bleed. If smaller apertures are required for SMT processes, the number of vias should be increased to maintain overall thermal resistance as low as possible.
In addition to vias in the pad area, thermal vias are also placed outside the IC body. For TSSOP packages, copper areas can extend beyond the package ends, providing an additional path for heat to escape through the top copper layer.
The perimeter pads of QFN devices prevent heat absorption via top copper layers; thermal vias must be used to dissipate heat to inner layers or the PCB bottom layer.
Figure 12 shows the PCB layout for a small QFN (4 × 4 mm) device, which only accommodates nine thermal vias in the exposed pad area. As a result, the thermal performance of this PCB is inferior to the TSSOP package shown in Figure 11.
Flip-Chip QFN (FCQFN) Package
The Flip-Chip QFN (FCQFN) package is similar to a standard QFN package, but the die is flipped and directly bonded to the pads at the bottom of the device instead of using bond wires to connect to package pads. These pads can be placed opposite high-power dissipation devices on the die, so they are typically arranged as long strips rather than small pads (see Figure 13).
These packages use multiple rows of copper bumps on the die surface to bond to the leadframe (see Figure 14).
Small vias can be placed within the pad area, similar to standard QFN packages. On multilayer boards with power and ground planes, vias directly connect these pads to the internal planes. In other cases, copper areas must be directly connected to the pads to draw heat from the IC into large copper regions.
Figure 15 shows MPS’s power-stage IC MP6540, which features long power and ground pads and three output ports, with a package size of only 5 mm × 5 mm.
The copper area on the left side of the device is the power input, directly connected to the two power pads of the device.
The three output pads connect to the copper area on the right side of the device; note that the copper area expands as much as possible after exiting the pads, maximizing heat transfer from the pads to the ambient air.
Note the rows of small vias in the two pads on the right side of the device. These pads are grounded, with a solid ground plane on the PCB backside. The vias have a diameter of 0.46 mm and a drill diameter of 0.25 mm, small enough to fit within the pad area.
In summary, successful PCB design with motor driver ICs requires careful layout. This article provides practical recommendations to help PCB designers achieve excellent electrical and thermal performance for PCBs.
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