To achieve high-quality PCB design, in addition to the overall routing and layout, the rules for line width and line spacing are also extremely critical, as they directly determine the performance and stability of the circuit board. Therefore, taking RK3588 as an example, this article introduces the general design rules for PCB line width and line spacing in detail.
To achieve high-quality PCB design, in addition to the overall routing and layout, the rules for line width and line spacing are also extremely critical, as they directly determine the performance and stability of the circuit board. Therefore, taking RK3588 as an example, this article introduces the general design rules for PCB line width and line spacing in detail.
It should be noted that before routing, the default setting options of the software must be configured, and the DRC (Design Rule Check) detection switch must be turned on. For routing, it is recommended to enable the 5mil grid, and the 1mil grid can be set according to actual conditions during length matching.
PCB Routing Line Width
Routing must first meet the processing capability of the fabrication factory. First, confirm the manufacturer with the customer and verify its production capacity, as shown in the table below. If the customer has no special requirements, the line width shall refer to the impedance design template.
| Item |
Prototype |
Mass Production |
| Minimum Line Width & Spacing |
3/3mil |
3/3mil |
| Impedance Control |
+/-5% |
+/-10% |
| Maximum Copper Thickness |
12oz |
12oz |
| Maximum Board Thickness to Hole Diameter Ratio |
10:1 |
10:1 |
| Maximum Board Size |
610mm × 1100mm |
- |
For the impedance template, select the appropriate impedance model according to the board thickness and layer count requirements provided by the customer, and set the routing line width according to the width calculated in the impedance model. Common impedances include 50Ω single-ended, 90Ω and 100Ω differential, etc. Attention should be paid to whether inter-layer reference should be considered for the 50Ω antenna signal. The layer stack-up of a common PCB is shown in the figure below.
As shown in the figure below, the routing line width must meet the current-carrying capacity. In general, based on experience and with routing margin considered, the power line width can be designed according to the following rules: with a temperature rise of 10°C, for 1OZ copper thickness, a 20MIL line width can carry an overcurrent of 1A; for 0.5OZ copper thickness, a 40MIL line width can carry an overcurrent of 1A.
In conventional design, the line width should be controlled above 4mil as much as possible, which can meet the processing capacity of most PCB manufacturers. For some designs that do not require impedance control (mostly 2-layer board designs), ensuring the line width above 8mil can reduce the PCB production and processing cost.
Routing shall take into account the copper thickness of the layer where it is located. For example, for 2OZ copper thickness, the line width should be designed above 6mil as much as possible. The thicker the copper, the wider the line width shall be. For designs with uncommon copper thickness, you can consult the processing requirements of the manufacturer.
For BGA (Ball Grid Array) designs with 0.5mm and 0.65mm pitch, a 3.5mil line width can be used in partial areas (managed by design area rules).
For HDI (High-Density Interconnect) board design, a 3mil line width can be selected. For designs with line width less than 3mil, the production capacity of the processing factory must be confirmed with the customer, as some manufacturers have a production capacity of 2mil. The finer the line width, the higher the processing cost and the longer the processing cycle.
Analog signals (such as audio and video signals) must be widened, generally to a line width of 15mil. If space is limited, the line width should be controlled above 8mil.
RF (Radio Frequency) signals shall be widened, with inter-layer reference and impedance controlled at 50Ω. RF signals shall be routed on the surface layer, avoid being routed on inner layers, and try to avoid via hole and layer transition. RF signals must be surrounded by ground, and the reference layer shall refer to the GND copper plane as much as possible.
PCB Routing Line Spacing
Routing must first meet the processing capacity of the factory, and the line spacing shall meet the production capacity of the factory, generally controlled above 4mil. For BGA designs with 0.5mm and 0.65mm pitch, a 3.5mil line spacing can be used in partial areas; for HDI designs, a 3mil line spacing can be selected. For designs with line spacing less than 3mil, the production capacity of the processing factory must be confirmed with the customer, as some manufacturers have a production capacity of 2mil (managed by design area rules).
Before designing the line spacing rules, the copper thickness requirements of the design must be considered. For 1OZ copper thickness, the spacing should be kept above 4mil as much as possible; for 2OZ copper thickness, the spacing should be kept above 6mil as much as possible.
For the spacing design within the differential signal pair, the corresponding spacing shall be reasonably set according to the impedance requirements.
Routing shall be kept away from the board outline. Try to ensure that the board outline area can be surrounded by ground with GND vias, and keep the signal more than 40mil away from the board edge.
The signal on the power layer shall be indented more than 10mil from the GND layer. The width between the power supply and the power copper plane shall be kept more than 10mil apart. For some ICs (such as BGA) with small pitch, the spacing can be appropriately adjusted to more than 6mil (managed by design area rules).
Important signals, such as clock, differential and analog signals, must meet the 3W distance requirement or be surrounded by ground. The spacing between lines shall be kept 3 times the line width. This is to reduce crosstalk between lines, and sufficient line spacing must be ensured. If the center-to-center distance between lines is no less than 3 times the line width, 70% of the electric field between lines can be kept from interfering with each other, which is called the 3W Rule, as shown in the figure below.
Signal routing on adjacent layers shall avoid parallel routing, and the routing direction shall adopt an orthogonal structure to reduce unnecessary inter-layer crosstalk. The figure below shows vertical and parallel routing.
When routing on the surface layer, it shall be kept away from the positioning holes with a distance of more than 1mm, to prevent short circuit during installation or open circuit caused by line tear due to installation stress. The figure below shows the keep-out area of the screw hole.
Attention shall be paid to the plane segmentation of the power layer: a power plane shall not be split too fragmented. The number of power signals processed in one power plane shall not exceed 5, and preferably be controlled within 3, to ensure the current-carrying capacity and avoid the risk of cross-segmentation of signals on adjacent layers, as shown in the figure below.
When segmenting the power layer, the width of the dividing line is specified as follows: when the voltage difference is greater than 12V, the dividing line width is 50mil; when the voltage difference is less than 12V, the dividing line width is 20~25mil.
The power plane segmentation shall be kept as regular as possible. Long and narrow strips and dumbbell-shaped segmentation are not allowed, to avoid the situation of large ends and small middle. The current-carrying capacity shall be calculated according to the width of the narrowest part of the power copper plane. The figure below shows the dumbbell-shaped segmentation of the power plane.
Intelligent Detection of PCB Line Width and Line Spacing
After the PCB design is completed, analysis and inspection must be performed to ensure smooth production. There are many analysis points for layout and routing. Here we recommend a tool that can perform one-click intelligent detection of the minimum PCB line width。
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