ESD-resistant design of PCBs can be realized through layer stacking, proper component layout, routing and assembly. In the design phase, most design modifications can be limited to adding or removing components through prediction. ESD protection can be effectively achieved by adjusting PCB layout and routing.
ESD-resistant design of PCBs can be realized through layer stacking, proper component layout, routing and assembly. In the design phase, most design modifications can be limited to adding or removing components through prediction. ESD protection can be effectively achieved by adjusting PCB layout and routing.
Static electricity from the human body, the environment, or even internal equipment can cause various damages to precision semiconductor chips, such as penetrating thin insulating layers inside components; destroying the gate electrodes of MOSFET and CMOS components; triggering latch-up of flip-flops in CMOS components; shorting reverse-biased PN junctions; shorting forward-biased PN junctions; melting bonding wires or aluminum wires inside active devices. To eliminate the interference and damage caused by Electrostatic Discharge (ESD) to electronic equipment, various technical measures must be adopted for protection.
ESD-resistant design of PCBs can be implemented through layer stacking, proper layout, routing and assembly. During the design process, most design changes can be restricted to component addition or removal by prediction. ESD can be well prevented by adjusting PCB layout and routing. The following are common preventive measures:
Use multi-layer PCBs as much as possible. Compared with double-sided PCBs, ground planes, power planes, and closely arranged signal line-ground line spacing can reduce common-mode impedance and inductive coupling to 1/10 to 1/100 of that of double-sided PCBs. Arrange each signal layer as close as possible to a power layer or ground layer. For high-density PCBs with components on both top and bottom surfaces, very short connecting wires, and extensive ground filling, inner-layer routing may be considered. For double-sided PCBs, adopt tightly interwoven power and ground grids. Place power lines close to ground lines, and make as many connections as possible between vertical/horizontal lines or filled areas. The grid size on one side shall be ≤60mm, and preferably less than 13mm if possible.
Ensure that each circuit is as compact as possible.
Place all connectors on one side as much as possible.
If possible, route power lines from the center of the card and keep them away from areas susceptible to direct ESD impact.
Place wide chassis ground or polygon ground fills on all PCB layers below connectors leading outside the chassis (vulnerable to direct ESD strikes), and connect them with vias at approximately 13mm intervals.
Place mounting holes on the edge of the card, and connect the top and bottom solder masks-free pads around the mounting holes to the chassis ground.
During PCB assembly, do not apply any solder on the top or bottom solder pads. Use screws with built-in washers to achieve tight contact between the PCB and the metal chassis/shield or brackets on the ground plane.
Maintain identical "isolation zones" between chassis ground and circuit ground on each layer; keep the spacing at 0.64mm if possible.
Connect chassis ground and circuit ground with 1.27mm-wide traces along the chassis ground line at 100mm intervals near the mounting holes on the top and bottom layers of the card. Place mounting pads or holes between chassis ground and circuit ground adjacent to these connection points. These ground connections can be cut open with a blade to keep open circuits, or jumpered with magnetic beads/high-frequency capacitors.
If the PCB is not installed in a metal chassis or shielding device, do not apply solder mask on the chassis ground lines of the top and bottom layers of the PCB, so that they can serve as discharge electrodes for ESD arcs.
Set up a ring ground around the circuit in the following ways:
(1) Arrange ring ground paths around the entire periphery except for edge connectors and chassis ground.
(2) Ensure that the ring ground width on all layers is greater than 2.5mm.
(3) Connect the ring ground with vias at 13mm intervals.
(4) Connect the ring ground to the common ground of the multi-layer circuit.
(5) For double-sided PCBs installed in metal chassis or shielding devices, connect the ring ground to the common circuit ground. For unshielded double-sided circuits, connect the ring ground to the chassis ground, and do not apply solder mask on the ring ground so that it can act as an ESD discharge bar. Leave at least one 0.5mm-wide gap on the ring ground (all layers) to avoid forming a large loop. The distance between signal routing and the ring ground shall not be less than 0.5mm.
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