ESD/EMI Protection Design Recommendations for RK3588 Products in PCB Layout

Core Definitions

• ESD (Electro-Static Discharge): A natural phenomenon of static electricity release, characterized by high voltage, low power, small current, and short action time, which easily causes instability or damage to electronic products.
• EMI (Electromagnetic Interference): High-speed signal lines, IC pins, and connectors can act as radiation interference sources, emitting electromagnetic waves to disrupt the normal operation of systems or sub-systems.

1. ESD Protection Design

1. Structural Isolation: Recess connectors into the housing to lengthen the static discharge path and weaken energy.
2. Sensitive Device Protection: Add shielding covers for sensitive modules (RF, audio, memory).
3. Core Component Layout: Place the RK3588 chip and core parts in the center of the PCB; ensure shielding covers are at least 2mm from the board edge and reliably grounded.
4. Modular Layout: Arrange components by functional modules and signal flow; isolate interference sources (e.g., DC-DC switching power supplies).
5. ESD Device Placement: Install ESD components at interfaces or static discharge points; route signals through ESD devices before drilling vias.
   
6. Spacing Rules: Keep components ≥20mil from the board edge and ≥40mil from connectors.
7. Grounding Design: Provide a complete GND loop on the surface layer; connect connectors and shielding covers to the surface ground with multiple ground vias at welding points; avoid routing or cutting ground copper near connectors.
8. Board Edge Treatment: Do not route signals on the surface board edge; add plenty of ground vias and isolate signals from ground if needed.
   
9. Copper Exposure: Expose copper in blank PCB areas to enhance static discharge.
   
10. Board-to-Board Connection: Series 2.2–10Ω resistors for signals and reserve TVS devices to improve anti-static surge capability.
11. RK3588 nPOR Pin: Place a 100nF capacitor close to the pin with at least one 8/16mil ground via (two or more if space allows).
12. Critical Signals: Keep reset, clock, interrupt signals ≥5mm from the board edge; provide a reference plane under routing to avoid edge effects.
    
13. Peripheral Chip Reset Pins: Add a 100nF capacitor close to the pin with ground vias for reliable grounding.
    
14. Regional Isolation: Use independent vias for connector ground pins to connect inner ground layers; isolate sensitive signals from static discharge areas on the surface layer.
    

2. EMI Protection Design

1. Interference Control: Address EMI by suppressing interference sources and cutting off coupling paths (the three elements of EMI: interference source, coupling channel, sensitive equipment).
   
2. Suppression Methods: Use filtering, grounding, impedance control, and termination; reliable grounding is fundamental.
3. EMI Components: Shielding covers, filters, resistors, capacitors, inductors, ferrite beads, common-mode chokes, wave-absorbing materials, and spread-spectrum devices.
4. Filter Selection: Use capacitive filters for high-impedance loads and inductive filters for low-impedance loads; apply common-mode chokes for differential interfaces.
5. Shielding Grounding: Ensure shielding structures are well-grounded to avoid radiation leakage or antenna effects.
6. Spread-Spectrum Clocking: Use module-level spread-spectrum for RK3588 per signal requirements.
7. Clock Matching: Retain series matching resistors for clocks and place them close to the CPU (routing ≤400mil).
8. Power Input Filtering: Reserve common-mode inductors or EMI filters at power inputs.
9. Interface Filtering: Add common-mode inductors or filter circuits for USB, HDMI, VGA, and display connectors.
10. Heatsink Design: Select heatsinks that meet both thermal and EMI requirements; reserve grounding points.
11. Common Rules with ESD: Most ESD layout rules apply to EMI; ensure signal integrity and symmetric, length-matched differential routing.
    
12. Layer Design: Route clocks on inner layers for PCBs with ≥4 layers; follow the 20H rule (power plane retracted by 1mm from the ground plane) to reduce radiation.