An In-depth Discussion on the Three Key Aspects of Power Integrity Design

Layout and Routing of Power Modules

1. Layout of Power Modules

• Source Processing: As the starting point of the power supply, the layout of the power module requires special attention. To minimize noise introduction, the surrounding environment of the power module should be kept as clean as possible, and it should be avoided to be adjacent to other high-frequency or noise-sensitive components.
• Close to Power Supply Chips: The power module should be placed as close as possible to the powered chips, which can reduce the loss during current transmission and lower the area requirement of the inner-layer planes.
• Heat Dissipation Considerations: Power modules may generate heat during operation, so there should be no obstructions above them to facilitate heat dissipation. If necessary, heat sinks or fans can be added for heat dissipation.
• Avoid Loops: Current loops should be avoided during routing to reduce the possibility of electromagnetic interference.

2. Routing of Power Modules

• Width and Current: The width of the power line should be determined according to the current it needs to carry; a larger current requires a wider line width to ensure current capacity.
• Number of Vias: If the power line needs to cross layers during routing, sufficient vias should be ensured to carry the current and avoid overheating of the vias.
• Distance and Coupling: An appropriate distance should be maintained between power lines and other signal lines to avoid coupling effects caused by excessive proximity.
• Ground Line Processing: As a return path, the ground line should ensure continuity as much as possible, avoiding breaks or sudden narrowing of the ground line.
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Design and Planning of Inner-layer Planes

1. Stack-up Design

• To ensure the low-impedance characteristic of the power plane and the ground coupling absorption of power noise, the distance between the power and ground planes should not exceed 10 mil, and it is usually recommended to be less than 5 mil.
• If a single power plane cannot be realized, the top layer can be used to lay the power plane. Adjacent power and ground planes form a planar capacitor with minimum AC impedance, which has excellent high-frequency characteristics.
• Avoid placing two adjacent power layers too close (especially those with large voltage differences) to prevent mutual noise coupling; if unavoidable, the distance between the two power layers should be increased as much as possible.
• Reference planes, especially power reference planes, should maintain low-impedance characteristics, which can be optimized through bypass capacitors and stack-up adjustments.

2. Division of Multiple Power Supplies

• For small-scale specific power supplies, such as the core operating voltage of a certain IC chip, copper laying on the signal layer is recommended as much as possible to ensure the integrity of the power layer; however, power copper laying on the top layer should be avoided to reduce noise radiation.
• The division width should be selected appropriately: for voltages above 12V, the width can be 20-30 mil; otherwise, 12-20 mil is recommended. The division width between analog and digital power supplies needs to be increased to prevent noise interference from digital power supplies to analog power supplies.
• Simple power supply networks should be completed on the routing layer, while longer power supply networks need to be equipped with filter capacitors.
• The divided power planes should maintain regular shapes to avoid resonance and increased power impedance caused by irregular shapes; slender strip and dumbbell-shaped divisions are not allowed.

3. Plane Filtering

• The power plane should be tightly coupled with the ground plane.
• For chips with an operating frequency exceeding 500 MHz, filtering should mainly rely on planar capacitors, and combined capacitor filtering should be adopted; the filtering effect needs to be confirmed through power integrity simulation.
• Control the mounting inductance of plane decoupling capacitors, such as widening capacitor leads and increasing capacitor vias, to ensure that the power-ground impedance is lower than the target impedance.

Layout and Routing of Power Supply Chips

1. Routing Processing of Chip Power Pins

2. Layout and Routing of Decoupling Capacitors

• Large Capacitors: Large capacitors are usually evenly distributed around the chip. Due to their low resonant frequency and large filtering radius, they can effectively filter low-frequency noise and provide a stable power supply.
• Small Capacitors: Small capacitors have a high resonant frequency and a small filtering radius, so they should be placed as close as possible to the chip pins. If placed too far away, they may not effectively filter high-frequency noise and lose the decoupling effect.

3. Routing Method for Parallel Multiple Decoupling Capacitors