PCB Layout and Routing Requirements for USB2.0 and USB3.0 Interfaces

Figure 1 Pin Definitions of USB 2.0 and USB 3.0 Interfaces

I. PCB Layout Requirements for USB Interfaces

1. The USB interface shall be placed close to the board edge or structural positioning, with a certain position protruding from the board edge (except for through-hole types), to facilitate plugging and unplugging.
2. ESD and common mode inductor components shall be placed close to the USB interface, in the order of ESD → common mode inductor → resistor and capacitor.
3. Attention shall be paid to the distance between the ESD device and the USB interface, with a certain spacing reserved to take into account the post-soldering process.
4. During layout, the differential line length shall be minimized as much as possible to shorten the distance of the differential pair.

II. PCB Routing Requirements for USB Interfaces

1. USB signals must be routed as differential pairs, with impedance controlled at 90 ohms and ground wrapping treatment applied. The total length should preferably not exceed 1800mil.
2. Minimize the trace length as much as possible, and give priority to the routing of high-speed USB differential pairs (RX and TX differential pairs). When routing USB differential traces, minimize the number of layer transition vias as much as possible, to achieve better impedance control and avoid signal reflection.
3. Vias will cause impedance discontinuity of the line. A pair of return ground vias shall be added at each layer transition position via drilling for signal return during layer switching.
4. If the positioning posts on both sides of the USB are connected to the protective ground, ensure a distance of 2mm from the signal GND during plane splitting, and place multiple vias in the protective ground area to ensure sufficient connection, as shown in Figure 2.

Figure 2 Isolation Between Chassis GND and Signal GND

5. Due to factors such as pin distribution, vias and routing space, the length of differential lines is prone to mismatch. Once the routing length is mismatched, timing deviation will occur, which will also cause common mode interference and reduce signal quality. Therefore, corresponding compensation shall be made for the mismatch of the differential pair to achieve line length matching. The length difference is usually controlled within 5mil, and the compensation shall be carried out in accordance with the differential length matching specification.

Figure 3 Layout and routing of USB 2.0


Figure 4 Layout and Routing of USB 3.0

III. PCB Design for Type C Interface

PCB Design Requirements for Type C Interface:

1. ESD and common mode inductor components shall be placed close to the Type C interface, in the order of ESD → common mode inductor → resistor and capacitor. Attention shall also be paid to the distance between the ESD device and the Type C interface, with a certain spacing reserved to take into account the post-soldering process.
2. The coupling capacitors of TX signal lines shall be placed close to the interface, and the coupling capacitors of RX signal lines are provided by the device end, as shown in Figures 7-24.

Figures 7-24 Coupling Capacitors for TX Signal Lines

2. The impedance of Type C differential traces is controlled at 90ohm±10%. To ensure impedance continuity, a complete reference plane shall be provided without crossing plane splits, and the number of layer transition vias for signal routing shall not exceed 2.
3. Type-C has four groups of differential signals (RX/TX1-2) and two groups of differential signals (D+/D-), totaling six differential pairs. The differential signal lines are required to be adjacent to at least one ground plane, preferably adjacent to ground planes on both sides. The traces shall be as short as possible, with the maximum length not exceeding 6 inches.
4. Ensure the length matching of Type C differential lines, with the intra-pair length matching error <6mil, and the length matching shall be carried out in accordance with the differential length matching specification.
5. To avoid the impact between Type C differential pairs or between differential pairs and other signals, the spacing between pairs is recommended to be ≥4 times the Type C trace width, and the spacing from other signals shall be kept ≥4 times the Type C trace width as much as possible.
6. CC1/CC2 are two key pins with multiple functions: connection detection, front and back side identification, DFP and UFP distinction (i.e., master-slave configuration), and Vbus configuration. The traces shall be widened during routing.

Figure 7-25 Routing Schematic of Type-C Connector

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