How to Perform Layout and Routing for DDR Module Circuit PCB Design

In the previous article, we discussed the importance of power supply PCB design. In this article, we will share PCB design recommendations for memory, and take RK3588, which you are most familiar with, as an example to introduce in detail how to perform layout and routing for the PCB design of DDR module circuits.

Since the maximum rate of the RK3588 DDR interface reaches 4266Mbps, which brings high difficulty to PCB design, it is strongly recommended to use the DDR template and corresponding DDR firmware provided by Rockchip's original manufacturer. The DDR template is released after rigorous simulation and test verification.

If the PCB design space of the single board is sufficient, priority should be given to reserving the layout and routing space required by the DDR circuit module, and copying the DDR template provided by Rockchip's original manufacturer, including keeping the relative position between the chip and DDR particles, the position of power supply filter capacitors, and copper pour spacing completely consistent.

If you design the PCB by yourself, please refer to the following PCB design recommendations. It is strongly recommended to perform simulation optimization, and then confirm with Rockchip's original factory FAE. After confirming that there is no problem, proceed to prototyping and debugging.

For the number of GND vias corresponding to the CPU pins, it is recommended to strictly refer to the template design, and the GND vias must not be deleted. For the 8-layer through-hole PCB template, the GND via design of the CPU pins is shown in the figure below, with yellow for DDR pin signals and red for ground pins.

Before and after signal layer transition, when the reference layers are all GND planes, GND return vias shall be added within the range of 25mil from the signal via (center-to-center spacing between vias) (yellow for DDR signals, red for GND signals) to optimize the signal return path. The GND vias must connect the GND reference planes before and after the signal layer transition.

One signal via shall be matched with at least one GND return via. Increasing the number of GND return vias as much as possible can further improve the signal quality, as shown in the figure below.

The position of GND vias and signal vias will affect the signal quality. It is recommended to place GND vias and signal vias in a staggered arrangement, as shown in the figure below. Although there are also 4 GND return vias, the situation where 4 signal vias are placed together shall be avoided, as the via crosstalk is the largest in this case.

For 8-layer boards, it is recommended that DDR signals be routed on Layer 1, Layer 6 and Layer 8. DQ, DQS, address and control signals, and CLK signals shall all refer to the complete GND plane. An incomplete GND plane will cause a significant impact on signal quality.

As shown in the figure below, when the signal reference layer is broken due to vias, GND traces can be used to optimize the reference layer and improve signal quality.

The crosstalk of the winding itself will affect the signal delay. Pay attention to the requirements shown in the figure below when performing length-matched serpentine routing.

Serpentine trace is a type of routing method often used in Layout. Its main purpose is to achieve timing matching. Designers must first understand that serpentine traces will damage signal quality and change transmission delay, and their use shall be avoided as much as possible during routing. However, in actual design, it is often necessary to intentionally perform winding to ensure sufficient hold time of the signal, or to reduce the time offset between signals in the same group. When routing differential pairs, attention should be paid to increasing the distance (S) between parallel line segments as much as possible, which is generally required to be at least greater than 3W.

When performing length matching, the delay of vias must be considered, as shown in the figure below.

Non-functional pads will damage the copper plane and increase the parasitic capacitance of vias. It is required to remove the non-functional pads of vias and adopt non-functional pad removal design.

The closer the trace is to the via, the worse the reference plane performance. It is recommended that the distance between the trace and the via drilling hole be ≧8mil, and the spacing should be increased where there is space.

Adjust the via position to optimize the cracks of the plane, avoid plane splitting, so as to optimize the return path, as shown in the figure below.

Ground wrapping shall be performed for DQS, CLK and WCLK signals. For the ground wrapping trace or copper plane, it is recommended to place a GND via at an interval of ≦400mil, as shown in the figure below.

For the VDD_DDR power supply, when the power supply transitions between layers in the DC-DC region, it is recommended to place ≧6 vias of 0503 package.

For the VDDQ_DDR power supply, when the power supply transitions between layers in the DC-DC region, it is recommended to place ≧6 vias of 0503 package.

For the VDD2_DDR power supply, when the power supply transitions between layers in the DC-DC region, it is recommended to place ≧6 vias of 0503 package.

For the VDD1_1V8_DDR power supply, when the power plane transitions between layers, it is recommended to place at least ≧2 vias of 0402 package.

It is recommended that each capacitor pad be matched with at least one via. For capacitors in 0603 or 0805 package, it is recommended that one pad correspond to two vias. The vias shall be placed close to the pins to reduce loop inductance.

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